1. Field of the Disclosure
Embodiments of the disclosure generally relate to methods for forming a dielectric layer with minimum contribution to lithographic overlay errors, more specifically, methods for forming a dielectric layer with minimum contribution to lithographic overlay errors used in gate stack materials for semiconductor applications.
2. Description of the Related Art
In the manufacture of integrated circuits (IC), or chips, patterns representing different layers of the chip are created by a chip designer. A series of reusable masks, or photomasks, are created from these patterns in order to transfer the design of each chip layer onto a semiconductor substrate during the manufacturing process. Mask pattern generation systems use precision lasers or electron beams to image the design of each layer of the chip onto a respective mask. The masks are then used much like photographic negatives to transfer the circuit patterns for each layer onto a semiconductor substrate. These layers are built up using a sequence of processes and translate into the tiny transistors and electrical circuits that comprise each completed chip. Typically, devices on semiconductor substrates are manufactured by a sequence of lithographic processing steps in which the devices are formed from a plurality of overlying layers, each having an individual pattern. Generally, a set of 15 to 100 masks is used to construct a chip and can be used repeatedly.
Between one layer and the next layer that overlays the previous one, the individual patterns of the one layer and the next layer must be aligned. A measurement of alignment marks may be obtained by a metrology tool which is then used by a lithography tool to align the subsequent layers during exposure and again after a lithography process to recheck a performance of the alignment. However, overlay errors (or pattern registration errors) between layers are inevitable, and error budgets are calculated by IC designers for which the manufacturing must meet. Overlay errors of the device structure may originate from different error sources, such as overlay errors from previous exposure tool/metrology tool, substrate warpage, current exposure tool/metrology tool limitation, a matching error between the overlay errors of the previous exposure tool/metrology tool and of the current exposure tool/metrology tool, or substrate film layer deformation caused by film stress and the like.
FIG. 1 depicts an overlay error map 100 of a semiconductor substrate measured after a sequence of lithographic exposure processes. In the embodiment of FIG. 1, some patterns shown in an enlarged portion 102 of the substrate are shifted or displaced, e.g., in-plane displacement (IPD), from their designed location. As discussed above, displacement or misalignment of the patterns creates overlay errors that may be detriment to device performance. However, when overlay errors or in-plane displacement (IPD) undesirably occurs, the size, dimension or structures of dies formed on the substrate may be irregularly deformed or distorted, thus increasing likelihood of misalignment between the film layers stacked thereon that may adversely increase the probability of misalignment in the subsequent lithographic exposure process.
With the shrink of critical dimensions (CD), overlay error in the critical layers of the device structure must be minimal or eliminated in order to reliably produce devices with minimal feature sizes, such as a width of a control gate in a device. Overlay specifications have become more challenging that the non-lithographic contributions (i.e., film stress) to overlay errors through stress induced substrate distortion, may alone exceed the error budget.
Therefore, there exists a need for improved methods and system to minimum overlay errors for film layers formed for manufacturing the devices so as to improve device performance and maintain predicable product reliability and yield.